Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applicability and numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG. 1. The device generally includes a gate electrode 101, which acts as a conductor, to which an input signal is typically applied via a gate terminal (not shown). Heavily doped source 103 and drain 105 regions are formed in a semiconductor substrate 107 and are respectively connected to source and drain terminals (not shown). A channel region 109 is formed in the semiconductor substrate 107 beneath the gate electrode 101 and separates the source 103 and drain 105 regions. The channel is typically lightly doped with a dopant type opposite to that of the source 103 and drain 105 regions. The gate electrode 101 is physically separated from the semiconductor substrate 107 by an insulating layer 111, typically an oxide layer such as SiO.sub.2. The insulating layer 111 is provided to prevent current from flowing between the gate electrode 101 and the semiconductor source region 103, drain region 105 or channel region 109.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode 101, a transverse electric field is set up in the channel region 109. By varying the transverse electric field, it is possible to modulate the conductance of the channel region 109 between the source region 103 and drain region 105. In this manner an electric field controls the current flow through the channel region 109. This type of device is commonly referred to as a MOS field-effect-transistors (MOSFET).
Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices. In order to increase the capability of such electronic devices, it is necessary to integrate even larger numbers of such devices into a single silicon wafer. As the semiconductor devices are scaled down (i.e., made smaller) in order to form a larger number of devices on a given surface area, the structure of the devices and fabrication techniques used to make such devices must be altered.
One important step in the manufacture of MOS devices is the formation of the gate electrode and gate insulating layer. The gate insulating layer is typically formed by growing or depositing a thin oxide (referred to as a gate oxide) over the substrate. The gate electrode is typically formed by depositing, usually through chemical vapor deposition (CVD), a layer of polysilicon over the gate oxide, patterning the polysilicon using a mask and etching, typically through a dry etch process, the polysilicon to form gate electrodes. The gate electrodes may be doped by doping the polysilicon layer prior to gate electrode etch with an appropriate type dopant (e.g., arsenic or phosphorus for an n-type device and boron for a p-type device). Alternatively, the gate electrodes may be doped in conjunction with the formation of the source/drain regions.
One particular problem with polysilicon gate electrodes is the tendency for the gate dopant (e.g., arsenic or boron) to diffuse into the gate oxide layer and, in some cases, through the gate oxide layer and into the channel region beneath the gate electrode. Such diffusion of the gate dopant can have a deleterious impact on device performance. To inhibit such diffusion of gate dopants, nitrogen-bearing gate oxides are often formed, for example, by growing the gate oxide in a nitrogen bearing ambient. The nitrogen in the gate oxide does tend to inhibit the diffusion of the gate dopant. The nitrogen in gate oxide, however, presents other problems. For example, the nitrogen often tends to upwardly diffuse into lower regions of the gate electrode. This inhibits doping of the lower regions of the gate electrode with the gate dopant and forms after a depletion layer in the gate electrode, negatively impacting the performance of the device.